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Cover image for Safe operating area limits for power transistors

Safe operating area limits for power transistors

Location Call # Status
Joyner - Fed Docs Stacks C 13.10:400-44 ✔ Available
Cover image for Measurement of transistor scattering parameters

Measurement of transistor scattering parameters

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Joyner - Fed Docs Stacks C 13.10:400-5 ✔ Available
Cover image for A reverse-bias safe operating area transistor tester

A reverse-bias safe operating area transistor tester

Location Call # Status
Joyner - Fed Docs Stacks C 13.10:400-54 ✔ Available
Cover image for Large scale integration digital testing

Large scale integration digital testing

Location Call # Status
Joyner - Fed Docs Stacks C 13.46:1102 ✔ Available
Cover image for Microelectronic processing laboratory at NBS

Microelectronic processing laboratory at NBS

Location Call # Status
Joyner - Fed Docs Stacks C 13.10:400-53 ✔ Available
Cover image for Evaluation of an electronic load for pulsed current characterization of power semiconductors

Evaluation of an electronic load for pulsed current characterization of power semiconductors

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Cover image for Impact of accelerated stress-tests on SIC MOSFET precursor parameters

Impact of accelerated stress-tests on SIC MOSFET precursor parameters

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Cover image for RF and microwave modeling and measurement techniques for field effect transistors

RF and microwave modeling and measurement techniques for field effect transistors

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Cover image for Proceedings

Proceedings

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Cover image for Low-temperature operation of a Buck DC/DC converter

Low-temperature operation of a Buck DC/DC converter

  • 1995
  • Format: Book
Location Call # Status
Joyner - Microforms B300 NAS 1.15:107021 ✔ Available