Innovative Architecture for Future Generation High-Performance Processors and Systems 1999 International Workshop on Innovative Architectures (IWIA '99), November 1-3, 1999, Maui, Hawaii

Author/creator Veidenbaum, Alex Author Editor
Format Electronic
Publication InfoLos Alamitos : IEEE Computer Society Press
Description630 p. ill 28.000 x 022.000 cm.
Supplemental ContentFull text available from IEEE Electronic Library (IEL) Conference Proceedings
Supplemental ContentFull text available from IEEE Electronic Library (IEL)
Subjects
Computer Architecture

Other author/creatorNakashima,Hiroshi Author Editor
Other author/creatorNational Science Foundation Staff.
Other author/creatorMaui High Performance Computing Center Staff.
Other author/creatorIEEE Xplore (Online service)
Summary Annotation Papers from a September 2000 conference focus on issues of computer system design and applications, processor architecture, logic and circuit design, tools and methodology, and verification and testing. Papers are arranged in sections on new architectures, fault-simulation and ATPG at different design levels, advanced design techniques, improving CPU performance, parasitic modeling, low power and arithmetic, servers and parallelism, circuit optimization and analysis, and logic circuit families. Other themes include intelligent memory, processor microarchitecture, digital logic techniques, embedded processors, floorplanning and partitioning, basic algorithms in verification and test, advancements in DSP architecture, and logic optimization. Lacks a subject index. Annotation copyrighted by Book News, Inc., Portland, OR
Access restrictionAvailable only to authorized users.
Technical detailsMode of access: World Wide Web
Genre/formElectronic books.
LCCN 00103357
ISBN9780769508016
ISBN0769508014 (Trade Cloth) Active Record
Standard identifier# 9780769508016
Stock number00029433

Availability

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Electronic Resources ✔ Available