Microarchitecture (Micro-33 2000) 33rd Annual International Symposium
| Author/creator | Institute of Electrical and Electronics Engineers, Inc. Staff |
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | I E E E [Imprint] Los Alamitos : IEEE Computer Society Press |
| Description | 380 p. 28.000 x 022.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Subjects |
| Summary | Annotation Contains 31 papers from the December 2000 symposium that present emerging research in high-performance processor microarchitecture, embedded microarchitecture, and compiler optimization. The major areas of discussion are memory hierarchy, superscalar architecture, compilation, accelerator architecture, low-power design, and dynamic translation and multithreading. Some of the topics are predictor- directed stream buffers, modulo scheduling for a fully-distributed clustered VLIW architecture, dynamic cache compression for cache energy reduction, and increasing the size of atomic instruction blocks using control flow assertions. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| ISBN | 9780769509242 |
| ISBN | 076950924X (Trade Paper) Active Record |
| Standard identifier# | 9780769509242 |
| Stock number | 00029433 |
Availability
| Library | Location | Call Number | Status | Item Actions |
|---|---|---|---|---|
| Electronic Resources | ✔ Available |