17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)
| Author/creator | IEEE Computer Society Staff |
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | 456 p. 22.000 x 015.000 cm. |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Subjects |
| Summary | Annotation These 45 papers from the November 2002 symposium discuss techniques to assess and enhance the yield, reliability, and availability of VLSI systems. Several of the contributors present new approaches to fault simulation and injection, concurrent error detection, yield prediction, and sequential circuit design for testability. Specific topics include a simplified gate-level fault model for crosstalk effects analysis, input ordering in concurrent checkers to reduce power consumption, on-chip jitter measurement for phase locked loops, and a method to evaluate the repairability of embedded multiple regions DRAMs. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| ISBN | 9780769518312 |
| ISBN | 0769518311 (Trade Paper) Active Record |
| Standard identifier# | 9780769518312 |
| Stock number | PR01831 00029433 |
Availability
| Library | Location | Call Number | Status | Item Actions |
|---|---|---|---|---|
| Electronic Resources | ✔ Available |