Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty.
| Author/creator | Bahukudumbi, Sudarshan |
| Other author | Chakrabarty, Krishnendu. |
| Format | Electronic |
| Publication Info | Boston : Artech House, |
| Description | xv, 198 p. : ill. ; 24 cm. |
| Supplemental Content | Full text available from Ebook Central - Academic Complete |
| Subjects |
| Series | Artech House integrated microsystems series |
| Abstract | Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions. |
| Bibliography note | Includes bibliographical references and index. |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| LCCN | 2010455090 |
| ISBN | 9781596939899 |
| ISBN | 1596939893 |