Asian Test Symposium, 5th ATS 96
| Other author | IEEE Xplore (Online service) |
| Format | Electronic |
| Edition | 5th ed. |
| Publication Info | Los Alamitos : IEEE Computer Society Press |
| Description | 328 p. |
| Supplemental Content | Full text available from IEEE Conference Proceedings Archive |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) Conference Proceedings |
| Supplemental Content | Full text available from IEEE Electronic Library (IEL) |
| Subjects |
| Summary | Annotation Proceedings of the November 1996 symposium, with sessions on test pattern generation, board and system-level test, design for testability, concurrent error detection and fault tolerance, synthesis for testability, IDDQ and fault modeling, built-in self-test, circuit and system-level diagnostics, industrial applications, and practical issues. Specific subjects include test generation of analog switched- current circuits, realistic linked memory cell array faults, and minimal delay test sets for unate gate networks. No index. Annotation copyrighted by Book News, Inc., Portland, OR |
| Access restriction | Available only to authorized users. |
| Technical details | Mode of access: World Wide Web |
| Genre/form | Electronic books. |
| LCCN | 10817735 |
| ISBN | 9780818674785 |
| ISBN | 0818674784 (Trade Paper) Active Record |
| Standard identifier# | 9780818674785 |
| Stock number | 00029433 |
Availability
| Library | Location | Call Number | Status | Item Actions |
|---|---|---|---|---|
| Electronic Resources | Access Content Online | ✔ Available |